Contador en Verilog

module contador(clk, rst, en, ld, dataout);

input clk,rst,en,ld;
output reg [3:0] dataout;


always @ ( posedge clk)

begin

if (rst==1)
dataout= 4'b0000;

else if (en==1)
dataout=dataout;

else if (ld==1)
dataout=dataout+4'b0001;

else
dataout=dataout;

end

endmodule

/*`timescale 1ns/100ps
module Counter4 (reset, clk, count);

input reset, clk;
output count;
reg [3:0] count;

always @ (posedge clk) begin
if (reset) count = 4'b0;
else count = count + 4'b0001;
end

endmodule*/