Registro Verilog

module Registro_Ecualizador #(parameter width = 4)(
input clk44kHz,reset, enable,
input [width-1:0] datoIn,
output [width-1:0] datoOut
    );

reg [width-1:0] datoActual, datoSig;

always @ (posedge clk44kHz, posedge reset)

if (reset)
begin
datoActual <= 0;
datoSig <= 0;
end
else
datoActual <= datoSig;

always @*

begin
datoSig = datoActual;
if (enable)
datoSig = datoIn;
else
datoSig = datoActual;
end
assign dataOut = datoActual;

endmodule

Multiplicacion con deteccion de overflow

module Multiplicador #(parameter width = 4,Dec=2, Mag = width-Dec-1)(
input wire [width-1:0] A,B,
output reg [width-1:0] Result
    );

reg [2*width-1:0] Aux,AuxMul;//Realiza el resultado de las operaciones
reg [width-1:0] AuxA,AuxB;

localparam [width:0]//Extremos de los overflow
maximo = 2**(width-1)-1,
minimo = 2**(width-1)+1;

always @*//Realiza la multiplicacion y convierte A en positivo
begin
Aux = A*B;
if (A[width-1])//Si A fuese negativo se pasa a positivo
AuxA = -A;
else//Si A fuese positivo se queda asi
AuxA = A;
end

always @*
begin
if (B[width-1])//Si B fuese negativo se pasa a positivo
AuxB = -B;
else//Si B fuese positivo se queda asi
AuxB = B;
end

always @*
begin//El resultado de la multiplicacion
AuxMul = AuxA[width-2:0]*AuxB[width-2:0];//Obtiene la multiplicacion de los positivos
//Del auxiliar de la multiplicación se obtiene 2 magnitudes y la fraccion para que sea comparable con el maximo que tiene una magnitud y un decimal
if (AuxMul[2*Mag + 2*Dec -1 : Dec] > maximo)//Si se diera el caso de overflow
begin
if ( (A[width-1] == 1 && B[width-1] == 1) || (A[width-1] == 0 && B[width-1] == 0) )// Resultado positivo con overflow es el maximo
Result = maximo;
else
Result = minimo;
end
else//Resultado negativo con overflow es un minimo
Result = Aux[2*width-2-Mag:Dec];//Se trunca el resultado para ser representable
end


endmodule

Sumador con detector de overflow

module Sumador#(parameter Width = 25, Signo = 1, Magnitud = 8, Presicion = 16)// Parametros por senal
(A, B, Y);   //Entradas y salida

input [Width-1:0] A,B; //Definir entradas
output reg [Width-1:0] Y; //Define salidas
reg signed [Width-1:0] Aux; //Variable auxiliar para realizar calculos
reg signed [Width-1:0] maximo;
reg signed [Width-1:0] minimo;



//assign Aux = A+B; //Operación de suma

always @*
begin
Aux = A+B;
maximo = (2**(Width-1))-1;
minimo = (2**(Width-1))+1;
end

always @*
begin
if (~A[Width-1] && ~B[Width-1] && Aux[Width-1])     //Verificación de overflow
begin
//Y= 4'b1111;
//Y = (2**(Width-1))-1;
Y = maximo;
end

else if (A[Width-1] && B[Width-1] && ~Aux[Width-1]) //Verificación de overflow
begin
//Y=4'b1111;
//Y=(2**(Width-1))+1;
Y = minimo;
end

else
begin
Y = Aux;
end
end
endmodule

Simulacion de entrada de un dato para el Pmod AD1 nexys 3

module Simulacion_ADC_Instanciado;

// Inputs
reg clk100MHz;
reg reset;
reg datoADC;
reg inicio;

// Outputs
wire [15:0] dato_con_basura;
wire [11:0] dato_sin_basura;
wire listo;
wire CS;
wire clk44kHz;

// Instantiate the Unit Under Test (UUT)
ADC_DivisorFreq_Instanciado uut (
.clk100MHz(clk100MHz),
.reset(reset),
.datoADC(datoADC),
.inicio(inicio),
.dato_con_basura(dato_con_basura),
.dato_sin_basura(dato_sin_basura),
.listo(listo),
.CS(CS),
.clk44kHz(clk44kHz)
);

initial forever

#10 clk100MHz = ~clk100MHz;

initial begin
// Initialize Inputs
clk100MHz = 0;
reset = 0;
datoADC = 0;
inicio = 0;

#100000;

reset = 1;

#100000

reset = 0;

#100000

inicio = 1;

datoADC = 1; // bit basura    //Empezando con los MSBS
@(negedge clk44kHz)
datoADC = 1; // bit basura
      @(negedge clk44kHz)
datoADC = 1; // bit basura
@(negedge clk44kHz)
datoADC = 1; // bit basura
@(negedge clk44kHz)
datoADC = 0; // bit numero 12 del dato
@(negedge clk44kHz)
datoADC = 1; // bit numero 11 del dato
      @(negedge clk44kHz)
datoADC = 0; // bit numero 10 del dato
@(negedge clk44kHz)
datoADC = 1; // bit numero 9 del dato
@(negedge clk44kHz)
datoADC = 0; // bit numero 8 del dato
@(negedge clk44kHz)
datoADC = 1; // bit numero 7 del dato
      @(negedge clk44kHz)
datoADC = 0; // bit numero 6 del dato
@(negedge clk44kHz)
datoADC = 1; // bit numero 5 del dato
@(negedge clk44kHz)
datoADC = 0; //bit numero 4 del dato
@(negedge clk44kHz)
datoADC = 1; //bit numero 3 del dato
@(negedge clk44kHz)
datoADC = 0; //bit numero 2 del dato
@(negedge clk44kHz)
datoADC = 1; //bit numero 1 del dato
inicio = 0;
#100;
      repeat(10) @(posedge clk44kHz);
$stop;
end
endmodule

Capturar un dato de un Teclado mediante el Codigo de ruptura F0

module CapturarTeclado(
input wire [7:0] datoEntrada,
input wire rxListo,clk,reset,
output wire [7:0] datoListo
);


reg indicaF0,datoF0;
reg [7:0] datoSalida,datoSalidaListo;

always@(posedge clk,posedge reset)
begin
if(reset)
begin
indicaF0 <= 1'b0;
datoSalida <= 8'd0;
end
else
begin
indicaF0 <= datoF0;
datoSalida <= datoSalidaListo;
end
end

always@*
begin
datoSalidaListo <= datoSalida;
datoF0 <= indicaF0;

if (rxListo && datoEntrada == 8'hF0)
begin
datoF0 <= 1'b1;
end

else if (rxListo && indicaF0 && datoEntrada != 8'hF0)
begin
datoF0 <= 1'b0;
datoSalidaListo <= datoEntrada;
end
end

assign datoListo = datoSalida;


endmodule

Pmod AD1 Nexys 3

module Recibir_ADC #(parameter width =16)
(input wire clock44kHz,reset,
input wire datoADC,inicio,
output wire [11:0] Dato_sin_basura,
output wire [width-1:0] dout,
output wire CS_out,
output wire listo
    );

//symbolic state declaration

localparam [1:0]
idle = 2'b00,
dps  = 2'b01,
load = 2'b10;

//Signal declaration

reg [1:0] state_reg, state_next;
reg [4:0] n_reg, n_next;
reg [width-1:0] b_reg, b_next;
wire fall_edge;
reg f_ps2c_reg,CS,done;
wire f_ps2c_next;
reg [7:0] filter_reg;
wire [7:0] filter_next;
 // body
//=================================================
// filter and falling edge tick generation for ADC
//=================================================


always @ (posedge clock44kHz, posedge reset)
if (reset)
begin
filter_reg <= 0;
f_ps2c_reg <= 0;
end
else
begin
filter_reg <= filter_next;
f_ps2c_reg <= f_ps2c_next;
end

assign filter_next = {clock44kHz,filter_reg[7:1]};
assign f_ps2c_next = (filter_reg==8'b11111111) ? 1'b1:
(filter_reg==8'b00000000) ? 1'b0:
f_ps2c_reg;

assign fall_edge = f_ps2c_reg & ~f_ps2c_next;


//====================================================
//FSMD
//====================================================
//FSMD state & data registers

always @ (posedge clock44kHz, posedge reset)
if (reset)
begin
state_reg <= idle;
n_reg <= 0;
b_reg <= 0;
end
else
begin
state_reg <= state_next;
n_reg <= n_next;
b_reg <= b_next;
end

// FSMD next-state logic
always @*
begin
state_next = state_reg;
n_next = n_reg;
b_next = b_reg;
CS = 1'b1;
done =0;

case (state_reg)
idle:
if (inicio && CS)
begin
//shift in start bit
b_next = {datoADC, b_reg[width-1:1]};
n_next = 5'b10001;
CS = 1'b0;
state_next = dps;
end
dps: //8 data + 1 parity + 1 stop
if (~fall_edge)
begin
CS = 1'b0;
b_next = {datoADC, b_reg[width-1:1]};
if (n_reg==0)
state_next = load;
else
n_next = n_reg - 1;
end
load: // 1 extra clock to complete the last shift
begin
state_next = idle;
CS = 1'b1;
done = 1'b1;
end
endcase
end

//output

assign CS_out = CS;
assign dout = b_reg; // data bits
assign listo = done;
assign Dato_sin_basura = b_reg[11:0];
endmodule

Decodificador para escrbir mensajes en una LCD

module array(

input [7:0] In,
input switch,
output reg [7:0] Out
    );

// Este modulo es un decodificador que tiene como salida una LCD con el cual se escriben ciertos mensajes
always @*
begin
if (~switch)
begin
Out=8'b00110000;
Out=8'b00110000;
Out=8'b00110000;
Out=8'b00110000;
Out=8'b00000100;
Out=8'b00000001;
Out=8'b00000100;
Out=8'b00001111;
//Out=8'b00000001;


end
else
begin//always @ (In)
case (In)
8'b00000001 : Out = 8'b00000001; //CL
8'b00010001 : Out = 8'b11010100; //T
8'b00100001 : Out = 8'b11100101; //e
8'b00110001 : Out = 8'b11101101; //m
8'b01000001 : Out = 8'b11110000; //p
8'b01010001 : Out = 8'b11100101; //e
8'b01100001 : Out = 8'b11110010; //r
8'b01110001 : Out = 8'b11100001; //a
8'b10000001 : Out = 8'b11110100; //t
8'b10010001 : Out = 8'b11110101; //u
8'b10100001 : Out = 8'b11110010; //r
8'b10110001 : Out = 8'b11100001; //a
8'b11000001 : Out = 8'b10111010; //:
8'b11010001 : Out = 8'b10110010; //2
8'b11100001 : Out = 8'b10110011; //3
8'b11110001 : Out = 8'b11000011; //C

8'b00000010 : Out = 8'b00000001; //CL
8'b00010010 : Out = 8'b11010100; //T
8'b00100010 : Out = 8'b11100101; //e
8'b00110010 : Out = 8'b11101101; //m
8'b01000010 : Out = 8'b11110000; //p
8'b01010010 : Out = 8'b11100101; //e
8'b01100010 : Out = 8'b11110010; //r
8'b01110010 : Out = 8'b11100001; //a
8'b10000010 : Out = 8'b11110100; //t
8'b10010010 : Out = 8'b11110101; //u
8'b10100010 : Out = 8'b11110010; //r
8'b10110010 : Out = 8'b11100001; //a
8'b11000010 : Out = 8'b10111010; //:
8'b11010010 : Out = 8'b10110010; //2
8'b11100010 : Out = 8'b10110111; //7
8'b11110010 : Out = 8'b11000011; //C

8'b00000011 : Out = 8'b00000001; //CL
8'b00010011 : Out = 8'b11010100; //T
8'b00100011 : Out = 8'b11100101; //e
8'b00110011 : Out = 8'b11101101; //m
8'b01000011 : Out = 8'b11110000; //p
8'b01010011 : Out = 8'b11100101; //e
8'b01100011 : Out = 8'b11110010; //r
8'b01110011 : Out = 8'b11100001; //a
8'b10000011 : Out = 8'b11110100; //t
8'b10010011 : Out = 8'b11110101; //u
8'b10100011 : Out = 8'b11110010; //r
8'b10110011 : Out = 8'b11100001; //a
8'b11000011 : Out = 8'b10111010; //:
8'b11010011 : Out = 8'b10110010; //2
8'b11100011 : Out = 8'b10111001; //9
8'b11110011 : Out = 8'b11000011; //C

8'b00000100 : Out = 8'b00000001; //CL
8'b00010100 : Out = 8'b11010100; //T
8'b00100100 : Out = 8'b11100101; //e
8'b00110100 : Out = 8'b11101101; //m
8'b01000100 : Out = 8'b11110000; //p
8'b01010100 : Out = 8'b11100101; //e
8'b01100100 : Out = 8'b11110010; //r
8'b01110100 : Out = 8'b11100001; //a
8'b10000100 : Out = 8'b11110100; //t
8'b10010100 : Out = 8'b11110101; //u
8'b10100100 : Out = 8'b11110010; //r
8'b10110100 : Out = 8'b11100001; //a
8'b11000100 : Out = 8'b10111010; //:
8'b11010100 : Out = 8'b10110011; //3
8'b11100100 : Out = 8'b10110001; //1
8'b11110100 : Out = 8'b11000011; //C

8'b00000101 : Out = 8'b00000001; //CL
8'b00010101 : Out = 8'b11010100; //T
8'b00100101 : Out = 8'b11100101; //e
8'b00110101 : Out = 8'b11101101; //m
8'b01000101 : Out = 8'b11110000; //p
8'b01010101 : Out = 8'b11100101; //e
8'b01100101 : Out = 8'b11110010; //r
8'b01110101 : Out = 8'b11100001; //a
8'b10000101 : Out = 8'b11110100; //t
8'b10010101 : Out = 8'b11110101; //u
8'b10100101 : Out = 8'b11110010; //r
8'b10110101 : Out = 8'b11100001; //a
8'b11000101 : Out = 8'b10111010; //:
8'b11010101 : Out = 8'b10110011; //3
8'b11100101 : Out = 8'b10110101; //5
8'b11110101 : Out = 8'b11000011; //C

8'b00000110 : Out = 8'b00000001; //CL
8'b00010110 : Out = 8'b10100000; //__
8'b00100110 : Out = 8'b11000010; //B
8'b00110110 : Out = 8'b11100101; //e
8'b01000110 : Out = 8'b11100010; //b
8'b01010110 : Out = 8'b11100101; //e
8'b01100110 : Out = 8'b10100000; //__
8'b01110110 : Out = 8'b11010011; //S
8'b10000110 : Out = 8'b11101111; //o
8'b10010110 : Out = 8'b11101100; //l
8'b10100110 : Out = 8'b11101111; //o
8'b10110110 : Out = 8'b10100000; //__
8'b11000110 : Out = 8'b10111010; //:
8'b11010110 : Out = 8'b10101000; //(
8'b11100110 : Out = 8'b10100000; //__
8'b11110110 : Out = 8'b10100001; //!

8'b00001000 : Out = 8'b00000001; //CL
8'b00011000 : Out = 8'b10100000; //__
8'b00101000 : Out = 8'b11001101; //M
8'b00111000 : Out = 8'b11101111; //o
8'b01001000 : Out = 8'b11100100; //d
8'b01011000 : Out = 8'b11101111; //o
8'b01101000 : Out = 8'b10100000; //__
8'b01111000 : Out = 8'b11000101; //E
8'b10001000 : Out = 8'b11101101; //m
8'b10011000 : Out = 8'b11100101; //e
8'b10101000 : Out = 8'b11110010; //r
8'b10111000 : Out = 8'b11100111; //g
8'b11001000 : Out = 8'b10101110; //.
8'b11011000 : Out = 8'b10100000; //__
8'b11101000 : Out = 8'b10100000; //__
8'b11111000 : Out = 8'b10100000; //__

default :  Out = 8'b10100000; //:


endcase
end
end




endmodule